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Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

发表于 2015-01-01 来源 IET Information Security DOI 10.1049/iet-ifs.2013.0058

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作者

Wei He Shivam Bhasin Andres Otero Tarik Graba Eduardo de la Torre Jean-Luc Danger

单位

Centro de Electronica Industrial, Universidad Politecnica de Madrid, Jose Gutierrez Abascal, 2, 28006 Madrid, Spain;Department of COMELEC, Institut MINES-TELECO展开

Centro de Electronica Industrial, Universidad Politecnica de Madrid, Jose Gutierrez Abascal, 2, 28006 Madrid, Spain;Department of COMELEC, Institut MINES-TELECOM/TELECOM-ParisTech, CNRS LTCI(UMR 5141), 37/39 Rue Dareau, 75014 Paris, Franc

摘要

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the cou 更多..

balanced cell-based dual rail logic complementary nets compound gate synchronisation coprocessors correlation theory Cryptography differential power dual rail precharge logic dual rail structure electromagnetic analyses electromagnetic fields field programmable gate arrays fleld programmable gate array formal verification global precharge signal logic design logic gates network routing random-access storage routing repair tech security verification Side-channel analysis synchronisation

A formal study of two physical countermeasures against side channel attacks

发表于 2013-09-15 来源 Journal of cryptographic engineering DOI 10.1007/s13389-013-0054-6

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作者

Sébastien Briais Jean-Luc Danger Sylvain Guilley

单位

Secure-IC S.A.S.;;Institut Mines-Télécom, Télécom Paristech

摘要

Abstract:Secure electronic circuits must implement countermeasures against a wide range of attacks. Often, the protection against side channel attacks 更多..

BCDL COQ Dual-rail with precharge logics Formal proof Implementation-level countermeasures side-channel attacks WDDL

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography

发表于 2012-01-01 来源 International Journal of Reconfigurable Computing DOI 10.1155/2012/360242

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作者

Laurent Sauvage Sylvain Guilley Florent Flament Jean-Luc Danger Yves Mathieu

单位

Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault, F-75634 Paris Cedex 13, France;;Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault,展开

Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault, F-75634 Paris Cedex 13, France;;Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault, F-75634 Paris Cedex 13, France;;Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault, F-75634 Paris Cedex 13, France;;Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault, F-75634 Paris Cedex 13, France;;Télécom ParisTech, Institut Télécom CNRS LTCI, 46 rue Barrault, F-75634 Paris Cedex 13, France

摘要

Side channel and fault injection attacks are major threats to cryptographic applications of embedded systems. Best performances for these attacks are 更多..

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