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“S-Box” Implementation of AES Is Not Side Channel Resistant

发表于 2020-06-19 来源 Journal of Hardware and Systems Security DOI 10.1007/s41635-019-00082-w

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作者

grid.417971.d, 0000 0001 2198 7527, Department of Computer Science and Technology, Indian Institute of Technology Bombay, Mumbai, India grid.417971.d, 0000 0001 2198 7527, Department of Computer Science and Technology, Indian Institute of Technology Bombay, Mumbai, India grid.417971.d, 0000 0001 2198 7527, Department of Computer Science and Technology, Indian Institute of Technology Bombay, Mumbai, India grid.417971.d, 0000 0001 2198 7527, Department of Computer Science and Technology, Indian Institute of Technology Bombay, Mumbai, India

单位

grid.417971.d, 0000 0001 2198 7527, Department of Computer Science and Technology, Indian Institute of Technology Bombay, Mumbai, India

摘要

Several successful cache-based attacks have provided strong impetus for developing side channel resistant software implementations of AES. One of the 更多..

New cache designs for thwarting software cache-based side channel attacks

发表于 2007-06-09 来源 ACM SIGARCH Computer Architecture News DOI 10.1145/1273440.1250723

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作者

Zhenghong Wang Ruby B. Lee

摘要

Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target em 更多..

Cache Computer architecture processor security side channel timing attacks