作者
Sesibhushana Rao Bommana
Sreehari Veeramachaneni
Syed Ershad
MB Srinivas
单位
Department of Electrical & Electronics Engineering,BITS Pilani Hyderabad Campus,500078,Hyderabad,India;Department of Information Technology,Sri Sivasubramaniya展开
Department of Electrical & Electronics Engineering,BITS Pilani Hyderabad Campus,500078,Hyderabad,India;Department of Information Technology,Sri Sivasubramaniya Nadar College of Engineering,600020,Chennai,India;Department of Electronics and Communication Engineering,Aditya University,533437,Kakinada,India
摘要
This paper introduces a framework that combines Deep Learning (DL) models and Dynamic Partial Reconfiguration (DPR) in Field Programmable Gate Arrays 更多..
